As DRAMs increase in memory cell density, there is a continuing challenge to maintain sufficiently high storage capacitance despite decreasing cell area. Additionally, there is a continuing goal to further decrease cell area. One principal way of increasing cell capacitance is through cell structure techniques. Such techniques include three-dimensional cell capacitors, such as trenched or stacked capacitors.
A capacitor is comprised of two conductive plates separated by a non-conducting dielectric layer. The dielectric layer is preferably comprised of one or more materials having a very high dielectric constant and low leakage current characteristics. Example materials include SiO.sub.2 and Si.sub.3 N.sub.4. Si.sub.3 N.sub.4 is typically preferred due to its better dielectric properties than SiO.sub.2. Numerous other capacitor dielectric materials have been and are being developed in an effort to meet the increasingly stringent requirements associated with the production of smaller and smaller capacitor devices used in higher density integrated circuitry. Most of these materials do, however, add increased process complexity or cost over utilization of conventional Si.sub.3 N.sub.4 and SiO.sub.2 capacitor dielectric materials. Yet the smaller and thinner capacitors being produced in next generation DRAM density are reaching the limit of the utility of using Si.sub.3 N.sub.4 as a viable capacitor dielectric material.
Specifically, Si.sub.3 N.sub.4 is typically deposited by low pressure chemical vapor deposition (i.e., any chemical vapor deposition process at less than or equal to 100 Torr). This does, however, undesirably produce very small pin-holes through thin layers of less than 200 Angstroms. These pin-holes undesirably reduce film density and result in undesired leakage current in operation. Once developed, these leakage current inducing pin-holes are difficult to repair. One technique is to form the capacitor dielectric layer as a composite of a SiO.sub.2 /Si.sub.3 N.sub.4 /SiO.sub.2 composite. The strapping SiO.sub.2 layers are utilized principally to cure or plug the pin-holes formed in the Si.sub.3 N.sub.4. Conventional circuitry today provides the SiO.sub.2 /Si.sub.3 N.sub.4 /SiO.sub.2 composite layer to thicknesses approaching 150 Angstroms. However, it is difficult at best to obtain thinner composite layers which achieve desirable dielectric film properties for such capacitor dielectric layers.
An alternate process for producing a Si.sub.3 N.sub.4 layer having reduced pin-holes is by rapid thermal nitridation of a silicon layer utilizing a N.sub.2 or NH.sub.3 ambient. Such produces a considerably denser film having improved dielectric properties. However, the nitridation process is self limiting as the silicon from which the silicon nitride is created only derives from the outer silicon surface. This outer silicon surface is covered with silicon nitride during the initial nitridation. The nitrogen or ammonia is not capable of adequately diffusing through the initially formed silicon nitride to react with underlying silicon to produce more silicon nitride. Accordingly, the ultimate thickness of a silicon nitride film produced by nitridation is inherently self limited to thicknesses of less than 30 Angstroms. Such thickness is typically too low even for a substantially pin-hole free Si.sub.3 N.sub.4 layer to adequately function as a capacitor dielectric layer between two conductive capacitor plates.
One proposed technique for formation of Si.sub.3 N.sub.4 capacitor dielectric layers is to initially nitridize an outer silicon surface to obtain a 20 to 30 Angstrom thick layer. Subsequently, a silicon nitride film is deposited by low pressure chemical vapor deposition to achieve a desired overall thickness. Yet, the CVD deposited Si.sub.3 N.sub.4 layer will still inherently have lower density and an undesired amount of leakage current inducing pin-holes which adversely impacts the overall capacitor dielectric layer.
Accordingly, it would be desirable to produce improved methods which enable the production of thin Si.sub.3 N.sub.4 layer of adequate density to produce desired capacitor dielectric properties in a capacitor construction. Although the invention was principally motivated out of concerns associated with Si.sub.3 N.sub.4 films, the artisan will appreciate applicability of the invention to other materials.